Configurage data setup/hold timing circuit with user...

Details Configurage data setup/hold timing circuit with user... Configurage data setup/hold timing circuit with user...

2005-06-14

2005-06-14

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C327S277000, C327S284000

Reexamination Certificate

active

06907539

ABSTRACT:
An apparatus comprising a first delay circuit. The first delay circuit may be configured to present a data delayed signal having one of a plurality of delay times. The plurality of delay times may provide a user configurable setup/hold time.

REFERENCES:
patent: 5247617 (1993-09-01), Olson
patent: 5670904 (1997-09-01), Moloney et al.
patent: 6150863 (2000-11-01), Conn et al.
patent: 6310506 (2001-10-01), Brown
patent: 63177610 (1988-07-01), None
Dallas Semiconductor Datasheet, “DS1020 Programmable 8-Bit Silicon Delay Line”, Nov. 17, 1999.
IBM Technical Disclosure Bulletin; “Programmable Delay Line Control Signal Circuits”, vol. 37, No. 8, pp. 519-520, Aug. 1994.
JEDEC Standard No. 8-6, “High Speed Transceiver Logic (HSTL)—A1.5 V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits”, EIA/JESD8-6, Aug. 1995.

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