Clock generating apparatus for skew control between two-phase no

Details Clock generating apparatus for skew control between two-phase no Clock generating apparatus for skew control between two-phase no

1998-06-30

2000-06-06

Butler, Dennis M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

713503, 713600, G06F 112

Patent

active

060732466

ABSTRACT:
This invention provides a clock generating apparatus that can control a skew between two-phase non-overlapping clocks in order to maintain constant non-overlapping period through an accurate analysis for the clock skew by a simple programming of delay. The invention has a delay block that receives first and second clock signals as inputs, and outputs them with delay. The invention also can control every skew in the chip and non-overlapping period of the first and the second clock signal by constituting the delay block being programmable.

REFERENCES:
patent: 3745472 (1973-07-01), Garth
patent: 4165490 (1979-08-01), Howe, Jr. et al.
patent: 5258660 (1993-11-01), Nelson et al.
patent: 5307381 (1994-04-01), Ahuja
patent: 5455931 (1995-10-01), Camporese et al.
patent: 5465347 (1995-11-01), Chao et al.
patent: 5570045 (1996-10-01), Erdal et al.
patent: 5619157 (1997-04-01), Kumata et al.

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