1000 mb phase picker clock recovery architecture using interleav
Adaptive clock skew in a variably loaded memory bus
Adaptive data processing scheme based on delay forecast
Adaptive voltage scaling digital processing component and...
Adjustable byte lane offset for memory module to reduce skew
Adjustable byte lane offset for memory module to reduce skew
Adjustable data delay using programmable clock shift
Adjustable PCI asynchronous clock device
Adjusting and measuring the timing of a data strobe signal...
Amplifier with a fan-out variable in time
Apparatus and method for generating a delayed clock signal
Apparatus and method for generating a delayed clock signal
Apparatus and method for generating a delayed clock signal
Apparatus and method for generating a delayed clock signal
Apparatus and method for successively generating an event to...
Apparatus comprising clock control circuit, method of...
Apparatus coupling two circuits having different supply...
Apparatus for adjusting delay of a clock signal relative to...
Apparatus for aligning clock and data signals received from a RA
Apparatus for aligning clock and data signals received from...