Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2008-03-25
2008-03-25
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C713S500000, C713S600000
Reexamination Certificate
active
07350093
ABSTRACT:
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.
REFERENCES:
patent: 5560000 (1996-09-01), Vogley
patent: 5751655 (1998-05-01), Yamazaki et al.
patent: 5754838 (1998-05-01), Shibata et al.
patent: 5835956 (1998-11-01), Park et al.
patent: 5886918 (1999-03-01), Nakamura
patent: 6020773 (2000-02-01), Kan et al.
patent: 6061296 (2000-05-01), Ternullo, Jr. et al.
patent: 6151270 (2000-11-01), Jeong
patent: 6262938 (2001-07-01), Lee et al.
patent: 6359579 (2002-03-01), Chiang
patent: 6415339 (2002-07-01), Farmwald et al.
patent: 6542416 (2003-04-01), Hampel et al.
patent: 6552955 (2003-04-01), Miki
patent: 6553472 (2003-04-01), Yang et al.
patent: 6570800 (2003-05-01), Tanaka et al.
patent: 6621315 (2003-09-01), Heo et al.
patent: 2003/0218921 (2003-11-01), Schrogmeier et al.
patent: 2004/0260961 (2004-12-01), Zhao et al.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Perveen Rehana
Stoynov Stefan
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