Method and apparatus using parasitic capacitance for...
Method and bus system for synchronizing a data exchange...
Method and system for balancing clock trees in a...
Method and system for clock skew reduction in clock trees
Method and system for reducing the effects of simultaneously...
Method and system for selecting data sampling phase for self...
Method and system for selectively varying signal delay in...
Method and system of automatic delay detection and receiver...
Method for aligning clock and data signals received from a RAM
Method for aligning clock and data signals received from a RAM
Method for controlling timing in reduced programmable logic...
Method for determining if a delay required before proceeding...
Method for generating a skew schedule for a clock...
Method for receiver delay detection and latency minimization...
Method for reducing tuning etch in a clock-forwarded interface
Method for transferring data across different clock domains...
Method for transferring data across different clock domains...
Method of compensating for delay between clock signals
Method of integrated circuit design checking using...
Method of matching different signal propagation times...