Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
1999-12-30
2004-06-15
Gaffin, Jeffrey (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06751744
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit design checking; and more specifically, it relates to an efficient method for analyzing the timing, noise, and power consumption of logic networks in such integrated circuits prior to physically implementing the circuitry in hardware.
BACKGROUND OF THE INVENTION
Integrated circuit devices are comprised of large numbers of networks linked together to perform various logic functions. They are typically implemented in hardware form on silicon dies using solid state integrated circuit technology of which many types exist, very large scale integration (VLSI) being an example. A hierarchical implementation in such technology exists. The basic elements are the transistor, resistor, capacitor, or inductor, usually built in the silicon. One or more of these basic elements, or combinations thereof are electrically coupled to form the next higher elements, logic elements or gates, that perform simple to moderate logic tasks. When these elements are implemented in silicon, unwanted but often unavoidable parasitic elements such as capacitors, resistors, and inductors are created which can change the designed performance of higher order elements in the design. Other non-electrical elements such as mechanical linkages and thermal resistances may also be created and may have an effect on other aspects of the design, such as its reliability. In the next higher element, one or more gates are then electrically coupled to form logic networks that perform more complicated logical tasks. The electrical interconnection is implemented in hardware in conductive lines in wiring layers on the integrated circuit. The signals run from gate to gate in a network along these conductive wiring layers. Several problems arise in these interconnection designs that can adversely effect network or integrated circuit performance.
First the implementation of these wires introduces additional parasitic elements which can add unexpected delays to the signal propagation through the network. Second, signals running in one wire in close proximity to a second can couple and create a false signal on the second wire. Third, local voltage levels in the power grid can drop in some networks, making them more sensitive to noise on the signal wire. And fourth networks, circuit gates or even individual transistors and resistors can draw more current than anticipated because of duty cycle or other reasons, increasing power consumption. This increased power consumption often leads to local voltage drops which increase noise sensitivity.
Because it is expensive and time consuming to complete a physical implementation of integrated circuit design, find problems, redesign, and rebuild, it is advantages to do design analysis and design correction before implementation.
FIG. 1
is a flow diagram of outlining the general prior art method of integrated circuit design checking employed before first pass die layout is complete. The design is reduced to a design netlist
10
upon which circuit analysis
12
is performed. Design netlist
10
contained the circuit design information. The circuit analysis step
12
provides data so fixes can be calculated in step
14
, and changes made to the netlist
10
. The process is repetitive and much of the fix calculation is manual. As applied to timing analysis, this method uses estimated parasitics, supplied by the designer based on the designers prediction of relative placement of layout elements. Often this input is provided only for those networks where parasitics are believed to impact the critical timing.
FIG. 2
is a flow diagram outlining the general prior art method of integrated circuit design checking for analyzing time delays after first pass die layout is complete. The netlist
10
and a shapes file
16
are used to extract or calculate the parasitics in step
18
for each network in the design. Shapes file
16
contains the layout information. The circuit analysis software of step
12
then supplies data so the fixes can be calculated in step
14
. These fixes are fed back to the design netlist
10
and the shapes file
16
. While the flow of
FIG. 2
has the advantage of providing more accurate delay data, it is a very time consuming. Often this process is 7 times longer than the method of illustrated in FIG.
1
.
To illustrate the range of modeling that can be used for parasitic extraction the examples of
FIGS. 3 through 5
are instructive.
FIG. 3
is a schematic diagram of a simple network using a simple resistance/capacitance value to represent anticipated parasitic elements, as might be provided by a designer or a pre-layout estimation tool for analyzing timing delays through the network. In
FIG. 3
network
20
has input
22
stages
24
A,
24
B, and
24
C, and output
26
. The parasitic RC delay is modeled by the resistor
28
and capacitor
29
between stages
24
B and
24
C.
FIG. 4
is a schematic diagram of a simple network using a simple grounded capacitance parasitic elements for analyzing timing delays through the network. In
FIG. 4
network
30
has input
32
gates
34
A,
34
B, and
34
C, and output
36
. Designers can supply the parasitic as an RC delay comprised of grounded capacitors
38
A,
38
B and
38
C combined with the output impedances of stages
34
A,
34
B, and
34
C, respectively.
FIG. 4
is illustrative of another example typical of the parasitics that might be supplied by a designer or early estimation tool for the analysis shown in FIG.
1
and described above.
FIG. 5
is a schematic diagram of a simple network using a complex resistance and capacitance parasitics model for analyzing timing delays through the network;
FIG. 6
is a schematic diagram of a simple network. In
FIG. 5
network
40
has input
42
gates
44
and
46
and output
48
. The extracted parasitics include resistor/capacitor pairs
51
A/
51
B and
52
A/
52
B, which introduce additional delay between input
42
and gate
44
. The extracted parasitics further include resistor/capacitor pairs
53
A/
53
B,
54
A/
54
B, and
55
A/
55
B between gates
44
and
46
as well has line to line capacitor
50
, which also introduce additional delay. The extracted parasitics still further include resistor/capacitor pairs
56
A/
56
B,
57
A/
57
B, and
58
A/
58
B, which introduce additional delay between gate
46
and output
46
. This model, while supplying very accurate parasitics for delay or noise or power analysis, leads to very time consuming runs for the circuit analysis software used with this level of parasitic extraction. However simpler parasitic extractions as shown in
FIGS. 3 and 4
and described above, when applied to all nets, can reduce analysis accuracy to an unacceptable degree. The alternative of using manual selection of some networks for the complex models and others for simple parasitic extraction introduces the risk of human error.
In today's environment the size of elements on semiconductor devices is decreasing, thus the number of elements in an integrated circuit design are increasing making long run times longer and more unacceptable. At the same time, new technologies, circuit design styles, and scaling mean the impact of parasitics on timing, noise, and power grids is increasing and more accurate analysis is required. Therefore there exists a need for a method to provide accurate integrated circuit timing, noise and power design checking in less time.
SUMMARY OF THE INVENTION
The present invention provides a method of selectively reducing the complexity of individual network and combined network analysis in an integrated circuit design thus reducing runtimes, while controlling the loss of accuracy of the resulting analysis. The present invention employs a circuit analysis technique suitable for performing timing delay, noise sensitivity, or power consumption analysis.
The invention provides a method of selectively reducing the complexity of the extracted netlist, and thus analysis runtimes, while controlling the loss of accuracy of the resulting analysis. A preliminary anal
Allen Robert J.
Cohn John M.
Hathaway David J.
Cao Chun
Gaffin Jeffrey
International Business Machines - Corporation
Kotulak Richard M.
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