Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Patent
1998-10-30
2000-08-22
Heckler, Thomas M.
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
G06F 104, G06F 1200
Patent
active
061087955
ABSTRACT:
One embodiment of the present invention provides a method for aligning a data signal and a data clock signal received from a memory during a read operation. The method includes receiving the data signal and the data clock signal from the memory, and determining an offset between these signals. If the offset is outside of a valid range, the system adjusts a delay between the data clock signal and the data signal. In a variation on the above embodiment, the method is performed by special-purpose hardware located in a memory controller, and operates periodically while the computer system is running. In another variation, the method is carried out by a BIOS program stored in read only memory, and operates during system startup.
REFERENCES:
patent: 5623311 (1997-04-01), Phillips et al.
patent: 5726650 (1998-03-01), Yeoh et al.
patent: 6041419 (2000-03-01), Huang et al.
Heckler Thomas M.
Micro)n Technology, Inc.
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