Method of compensating for delay between clock signals

Details Method of compensating for delay between clock signals Method of compensating for delay between clock signals

2000-10-30

2004-11-02

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C713S401000, C713S500000, C713S501000, C713S502000, C713S503000, C713S600000, C713S601000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06813723

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for designing an integrated circuit, and more particularly, to a method of compensating for a delay between clock signals suitable for preventing improper data transmission caused by delay between clocks used in an integrated circuit.
2. Background of the Related Art
In general, the integrated circuit employs multi-clock system in which different clock signals are used. Of the various problems caused by use of the different clock signals, the improper data transmission is one of the problem.
A related art method of compensating for a delay between clock signals will be explained with reference to the attached drawings.
FIG. 1
illustrates a conceptual block diagram for explaining a related art method of compensating for a delay between clock signals, showing, as an example, a case when one clock signal is used.
Referring to
FIG. 1
, a related art device of compensating for a delay between clock signals is provided with scannable flipflops
11
and
11
a
, a combination circuit
13
, and a delay unit
15
. That is, the related art device of compensating for a delay between clock signals is provided with a first scannable flipflop
11
for receiving a data in response to a clock signal CLK, a combination circuit
13
connected to an output terminal on the first scannable flipflop
11
, a delay unit
15
for delaying the clock signal for compensating for a delay between clock signals, and a second scannable flipflop
11
a
for receiving a signal from the combination circuit
13
using a signal from the delay unit
15
as a clock signal. In this instance, the inconsistency of clocks caused by the delay unit
15
causes the improper data transmission. In order to compensate for this, appropriate number of delays are provided between each of the flipflops which has a delay time period shorter than a delay time period by the delay unit
15
, additionally.
A related art method of compensating for a delay between clock signals will be explained.
FIG. 2
illustrates a flow chart for explaining a related art method of compensating for a delay between clock signals.
Referring to
FIG. 2
, the related art method of compensating for a delay between clock signals starts with calculating a delay value ‘a’ between the scannable flipflops(S
201
). A target value ‘b’ between flipflops is subtracted from the delay value ‘a’ between the scannable flipflops, to obtain a resultant ‘c’(S
202
). The resultant ‘c’ is compared to ‘O’(S
203
), to fix a number ‘d’ of delays in the delay unit if the resultant ‘c’ is greater than ‘O’(S
204
). The number ‘d’ of delays is fixed with reference to kind of the delay ‘e’ and a delay time period ‘f’ per a delay. In other words, when the delay value between the flipflops is smaller than a value delayed by the delay unit, an appropriate number of delays are provided between the flipflops having the smaller delay value. A number ‘d’ of delays as many as the delays fixed thus is added to a netlist(S
205
), to provide the delay unit
15
shown in FIG.
1
. That is, a delay value ‘a’ between flipflops are calculated, for providing a delay buffer between all flipflops each of which has a delay value smaller than the target delay value. Thus, the application of a technology to a design of an integrated circuit which employs different clock signals leads to require many delays for scan test, in which technology a delay time period between each of flipflops is calculated, and an appropriate number of delays are added between the flipflops if the calculated delay time period is shorter than a desired value irrespective of the clock signals applied to respective scannable flipflops.
However, the related art method of compensating for a delay between clock signals has the following problems.
First, because no delay between clocks are taken into consideration when multi-clock is used in a normal state, test clock signals may not be uniform due to the delay between clocks during the scan test. The non-uniform test clock signals impede an accurate data transmission.
Second, the greater delay value between clocks when different clock signals are used leads to require more delays for use in the scan test. That is, the provision of many delays leads to have a greater integrated circuit.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of compensating for a delay between clock signals that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of compensating for a delay between clock signals, in which a small number of delays are added, for solving a non-uniformity of clock signals.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method of compensating for a delay between clock signals for a semiconductor integrated circuit having a plurality of devices synchronous to a plurality of clock signals includes the steps of (1) searching for devices between which a data transmission path is set up synchronous to different clock signals among the plurality of devices, and (2) adding a plurality of delays only to between the devices having the data transmission path set up therebetween for compensating for the delay coming from a difference of clock signals.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


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