Method and system for selecting data sampling phase for self...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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C713S503000

Reexamination Certificate

active

06839861

ABSTRACT:
An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.

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J.J. Pertzborn, IBM TDB “Digital Clock Synchronization Circuit”, vol. 22, pp. 311-314.

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