Method for improving a timing margin in an integrated...
Method of reducing computer module cycle time
Method of signal distribution based on a standing wave...
Method, apparatus, and system for high speed data transfer...
Method, apparatus, and system for high speed data transfer...
Methods and apparatus for extending a phase on an interconnect
Multiple internal phase-locked loops for synchronization of chip
Obtaining a phase error of a clock signal
One-wire approach and its circuit for clock-skew compensating
Parallel data communication having skew intolerant data groups
Parallel data communication realignment of data sent in...
Parallel redundancy encoding apparatus
PECL voltage DIMM with remote multi-module etch skew...
Phase frequency detector with limited output pulse width and...
Phase frequency detector with limited output pulse width and...
Placement and routing method for optimizing clock skew in...
Programmable logic devices with skewed clocking signals
Programmable logic devices with skewed clocking signals
Programmable skew clock signal generator selecting one of a...
Reduction of data skew in parallel processing circuits