Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2006-05-09
2006-05-09
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000, C713S501000, C713S502000, C713S400000, C713S401000, C710S305000, C710S307000
Reexamination Certificate
active
07043656
ABSTRACT:
Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect state machine. The counter state machine may assert a signal to the interconnect state machine that may cause the interconnect state machine to prolong one or more phases of the transaction.
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