Method for improving a timing margin in an integrated...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate

Reexamination Certificate

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C714S036000, C714S744000

Reexamination Certificate

active

06647507

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to computers and more particularly to system boards and computer chips.
2. Background Information
Since the advent of computers, computer scientists and engineers have strived to make computers operate faster. One feature of the computer that has remained critical is the time that it takes for data to be transmitted from one component to another component located on the computer board. For example, data may be transferred from the memory to the processor. To transfer data at high speeds and with fidelity, the data transfer must be coordinated in time with the clock signals. Clock signals determine when a data signal is sent and received. If the data signal is sent too early or too late or if the data is received too early or too late, the data may become corrupt. This is commonly referred to as excess clock-data skew.
A computer board solution is not feasible because the correct receive clock time (RCLK) of data and the correct transmit clock time (TCLK) of data may vary depending upon the computer board manufacturing variation. Therefore, what is needed is a way of checking the timing of the signals on the computer board.


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