Programmable logic devices with skewed clocking signals

Details Programmable logic devices with skewed clocking signals Programmable logic devices with skewed clocking signals

2006-09-12

2006-09-12

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S400000, C713S401000, C713S500000, C713S501000, C713S502000, C713S600000, C713S600000

Reexamination Certificate

active

07107477

ABSTRACT:
A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic device. By suitably adjusting the relative timing of the device elements, the circuit critical path lengths are effectively reduced leading to improved circuit frequency performance. Algorithms are provided for establishing clock skew values that lead to improved circuit performance. The algorithms are incorporated in computer aided design tools to enable automatic optimization of circuit designs.

REFERENCES:
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 6107826 (2000-08-01), Young et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6292016 (2001-09-01), Jefferson et al.
patent: 6323679 (2001-11-01), Robertson et al.
patent: 6487648 (2002-11-01), Hassoun
patent: 6538489 (2003-03-01), Nakano
patent: 6690224 (2004-02-01), Moore
patent: 6816979 (2004-11-01), Chen et al.
patent: 6862548 (2005-03-01), Chan
patent: 6873187 (2005-03-01), Andrews et al.
V. Betz, J. Rose, and A. Marquardt,Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, 1999, Chapter 3, pp. 37-61.
J. Cong and Y. Ding, FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,IEEE Transactions on CAD, Jan. 1994, pp. 1-12.
John P. Fishburn, Clock Skew Optimization,IEEE Trans. Computer, Jul. 1990, vol. 39, No. 8, pp. 945-951.
C. Leiserson, F. Rose, and J. Saxe, Optimizing synchronous circuitry,Journal of VLSI and Computer Systems, 1983, pp. 41-67.
C. Leiserson and J. Saxe, Retiming synchronous circuitry,Algorithimca, vol. 6(1), pp. 5-35, 1991.
D. Singh and S. Brown, The Case for Registered Routing Switches in FPGAs, FPGA 2001.
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, A Look at “Minimum” Delays, http://support.xilinx.com/xcell/xl21/xl21-40.pdf.
Singh et al., Constrained Clock Shifting for Field Programmable Gate Arrays, FPGA '02, Feb. 24-26, 2002, Monterey, California, USA.

Affiliated with

Also associated with

Rating

Programmable logic devices with skewed clocking signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable logic devices with skewed clocking signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable logic devices with skewed clocking signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3579227