Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2003-02-11
2009-02-24
Du, Thuan N (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C370S503000
Reexamination Certificate
active
07496780
ABSTRACT:
Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchronization signal for the macrocell's channels. Each channel has a counter that implements a state machine used to drive the multiplexing processing, where the state machine is reset to a specified state upon receipt of each synchronization pulse in the synchronization signal.
REFERENCES:
patent: 4596981 (1986-06-01), Ueno et al.
patent: 5694066 (1997-12-01), Shyong
patent: 6336192 (2002-01-01), Sakamoto et al.
Abel Christopher J.
Anidjar Joseph
Duggal Abhishek
Laturell Donald R.
Agere Systems Inc.
Du Thuan N
Mendelsohn Steve
Mendelsohn & Associates, P.C.
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