One-wire approach and its circuit for clock-skew compensating

Details One-wire approach and its circuit for clock-skew compensating One-wire approach and its circuit for clock-skew compensating

2001-04-27

2004-06-22

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S401000, C713S600000

Reexamination Certificate

active

06754841

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a one-wire clock-skew compensating method and a circuit for this method, and especially to such a method and a circuit used to solve the clock-skew problem in transmission of clock signals in a high-speed synchronous circuit such as of a CPU of a computer, in order that the clock of a remote circuit and the clock input of the system can be accurately synchronized.
DESCRIPTION OF THE PRIOR ART
To high-speed synchronous circuits, clock-skew may result errors in access of information; especially when the technology advances rapidly today, if there are errors in access of important information, serious damage may be induced. For example, the clock frequencies of CPUs of computers determine the rate of data processing in CPUs, the clock frequencies in I/O and memory buses determine the rate of data transmission, and the clock frequencies in networks determine the rate of data transmission. In view of this, clock-skew reduction issue will be more and more important in future.
Since the skews are subject to influences of process, voltage supply, temperature, and loading (PVTL), it will result in the uncertainty of the arrival of the clock signal at a given circuit storage element (such as a flip-flop), and thereby result in the error of access of information. Once the internal clocks in a multi-chip system become asynchronous, the data transfer between chips will fail, and this is especially the case of a large-size printed circuit board. Hence, one needs the skew-free apparatus to guarantee that the circuits will function properly in a machine time cycle.
Many approaches exist for dealing with clock synchronization. Phase locked loops (PLLs) and delay locked loops (DLLs) are the two modes most widely adopted to solve the clock-skew issue. Wherein, the PLLs has the function of frequency synthesizing, it has the problem of accumulation of phase difference though, and is more suitable for making a clock generator rather than for chip-to-chip compensation for the skew. Due to the board wiring and packaging, DLLs do not have the problem of accumulation of phase difference, rather, they have faster locking speed, thus are more stable and useful to compensate for the skew to solve the asynchronous problem of the chips on electric circuit boards.
Generally, the structure of a conventional clock-deskew buffer circuit with a DLL is shown in
FIGS. 1 and 2
. It contains mainly a DLL
1
, a plurality of internal buffers
2
, and a pair of wires
3
,
4
externally. Assuming that the two wires
3
,
4
are matched, then the phases of the reference clock and the remote one are equal, the DLL
1
can be used to insert a time delay to synchronize the output clock and the input clock, i.e., to have the same phase. Once there is mismatch between both wires
3
,
4
, it may result in the phase difference between the reference clock (CK
REF
) and the remote clock (CK
RMT
).
SUMMARY OF THE INVENTION
To solve the mismatch of the two wires, a clock-skew compensating method with a single wire with bidirectional buffers and a circuit structure for the method are proposed. The idea is based on the fact that the forward and reverse paths in transmission and receiving of signals respectively at the two ends of the single wire are of the same electrical length, i.e., propagation delay for sending and receiving signals is same. Therefore, a clock-deskew buffer composed of a DLL and a bidirectional buffer is provided in the front of the signal transmission end of the single wire, while the other end of the single wire is provided with a bidirectional buffer too. In this way, signals can be transmitted bidirectionally at the same time on the single wire. When a signal is transmitted from the clock-deskew buffer to the receiving bidirectional buffer in a way passing through the forward and reverse paths, the arrival time thereof can be accurately controlled, this can avoid errors in dealing with signals due to phase difference between the reference clock (CK
REF
) and the remote clock (CK
RMT
) as in conventional techniques.
The present invention will be apparent after reading the detailed description of the preferred embodiment thereof in reference to the accompanying drawings.


REFERENCES:
patent: 6131149 (2000-10-01), Lu et al.
patent: 6166572 (2000-12-01), Yamaoka
patent: 6463092 (2002-10-01), Kim et al.
patent: 6522188 (2003-02-01), Poole

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