Programmable skew clock signal generator selecting one of a...

Details Programmable skew clock signal generator selecting one of a... Programmable skew clock signal generator selecting one of a...

2005-10-25

2005-10-25

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S401000, C713S500000, C375S371000

Reexamination Certificate

active

06959397

ABSTRACT:
A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal Fφ0from a reference signal FrefA frequency accumulator (132, 152) is preloaded with a preload value PK1and receives one reference signal cycle as a clock signal, receives a constant K1as an input thereto, with the frequency accumulator (132, 152) having a maximum count KMAXand producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value PC1and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C1as an input thereto. The phase accumulator (136, 156) has a maximum count CMAXand produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal Frefand produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output Fφ1whose phase shift φ1relative to F0φis a function of PK1and PC1.

REFERENCES:
patent: 6320436 (2001-11-01), Fawcett et al.
patent: 6353649 (2002-03-01), Bockleman et al.
patent: 6614813 (2003-09-01), Dudley et al.
patent: 6768442 (2004-07-01), Meyers et al.
patent: 2003/0152181 (2003-08-01), Stengel et al.
Uyemura John P, CMOS Logic Circuit Design, 2002, Kluwer Academic Publishers, pp. 271-273.
Cypress Semiconductor Corporation, “RoboClock® CY7B9950: 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer,” Document #: 38-07338 Rev. *B, Mar. 4, 2003, Cypress Semiconductor Corporation, 3901 North First Street, San Jose, CA 95134.
Liu, Shen-Iuan, et al. “Low-Power Clock-Deskew Buffer for High-Speed Digital Circuits,” IEEE Journal of Solid-State Circuits, Apr. 1999, pp. 554-558, vol. 34, No. 4, Publisher Item Identifier S 0018-9200(99)02436-1.

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