Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Patent
1998-02-13
2000-05-02
Butler, Dennis M.
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
G06F 104
Patent
active
060584882
ABSTRACT:
A reduction of multichip module computer system cycle time is achieved by using a voltage regulator for power supply noise attenuation to reduce jitter. The circuit for doing this includes an active filter network circuit for use in the multichip module of a computer system which generates a quiet analog VDD coupled directly to ground by using the low impedance power supply distributions which already exist in the module. The active filter network permits taking the power supply voltage from the module and stepping it down to a voltage needed by a phased lock loop via an active filter, said active filter comprising an op-amplifier and a source follower and a large value on module capacitor for a resistor network. The capacitor and resistor network acts as a filter with a large time constant where noise appearing on VDD,MOD is completely attenuated by this high value capacitor and resistor network part of our active filter network.
REFERENCES:
patent: 5604466 (1997-02-01), Dreps et al.
patent: 5731965 (1998-03-01), Cheng et al.
"Phase-Locked-Loop Control of a Tuning Fork Oscillator" IBM Technical Disclosure Bulletin, vol. 22, No. 3, Aug. 1979, pp. 1088-1090.
Becker Wiren D.
Eckhardt James Patrick
McNamara Timothy Gerard
Muench Paul David
Augspurger Lynn L.
Butler Dennis M.
International Business Machines - Corporation
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