Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2006-10-10
2006-10-10
Cribbs, Malcolm D. (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000, C713S502000
Reexamination Certificate
active
07120817
ABSTRACT:
A closed-loop based timing signal distribution architecture includes at least one signal source coupled to a signal path disposed in a closed loop arrangement to facilitate generation of a standing wave signal within the signal path. In one embodiment, at least one receiver is coupled to the signal path to generate at least one digital clock signal based upon the standing wave signal.
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Chakravarty Sourav
Kobrinsky Mauro J.
List R. Scott
Cribbs Malcolm D.
Intel Corporation
Schwabe Williamson & Wyatt P.C.
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