Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2001-05-08
2004-12-14
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S500000, C713S503000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06832328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a placement and routing method for clock distribution circuits, a clock distribution circuit manufacturing method, a semiconductor device manufacturing method, a clock distribution circuit and a semiconductor device, and particularly to an improvement for precisely and easily adjusting the clock skew.
2. Description of the Background Art
In an LSI (Large-Scale Integrated Circuit), it is not easy to supply a clock at the same time to all sequential elements (e.g. flip-flops) included in the circuitry without causing time differences in arrival of the clock among the sequential elements receiving it. These time differences are called clock skew. Particularly, operating LSIs at high speed requires highly precise clock skew control in order to reduce the clock skew to a very small value.
Factors contributing to the clock skew include non-uniformity of positions of the sequential elements and non-uniformity of the interconnection capacitances due to differences in interconnection length among adjacent interconnections or differences in intersection ratio among inter-layer interconnections. Therefore, in order to design a clock distribution circuit with a small clock skew, it is desirable to first conduct the placement and routing of the circuitry which is supplied with the clock (the circuitry is referred to as load circuit in this specification) and then design the clock distribution circuit. However, since the clock distribution circuit is distributed over the entire area of the semiconductor chip, there is a basic contradiction that the placement and routing cannot be finally settled until the clock distribution circuit has been designed.
Known conventional layout design methods for clock distribution circuit include the technique described in Japanese Patent Application Laid-Open No. 9-269847 (1997). In this conventional technique, two or more driver elements having different characteristics are placed in each of the positions of the driver elements in the clock distribution circuit and the clock skew is controlled by selecting one of the two or the more.
FIG. 10
is a circuit diagram showing the structure of a clock distribution circuit before the clock skew has been adjusted by this conventional technique. In this clock distribution circuit, the input clock CLK is distributed through the predriver circuit
1
having cascade-connected driver elements
4
a
,
4
b
and
4
c
to the main driver circuit
2
having driver elements
4
d
to
4
i
. The main driver circuit
2
supplies the clock to the load circuit
3
having sequential elements
7
a
to
7
g
and clock interconnections connecting the main driver circuit
2
and the sequential elements
7
a
to
7
g
. The predriver circuit
1
in the first stage and the main driver circuit
2
in the final stage are cascade-connected.
FIG. 11
is a circuit diagram showing the structure of the clock distribution circuit obtained after the clock skew adjustment. In the example shown in
FIG. 11
, in order to adjust the clock skew, the driver elements
4
d
and
4
e
belonging to the main driver circuit
2
have been replaced by driver elements
5
a
and
5
b
having a larger driving capability and a larger input capacitance and the driver elements
4
g
and
4
h
have been replaced by driver elements
6
a
and
6
b
having a smaller driving capability and a smaller input capacitance.
FIG. 12
is a flowchart showing the procedure of placement and routing method for the above-described clock distribution circuit according to the conventional technique. In this method, the clock distribution circuit is designed first (S
1
) and the placement and routing of the entire chip including the clock distribution circuit follows (S
2
). In the step S
2
, the placement and routing of the clock distribution circuit is a temporary one. Next, the clock skew value is calculated (S
3
) and then whether the calculated clock skew exceeds a target value is checked (S
4
).
If the step S
4
decides that the clock skew exceeds the target value, some of the driver elements are replaced with other driver elements having different driving capabilities and different input capacitances to adjust the clock skew (S
5
). Then the placement and routing is corrected as required by the replacement of the driver elements (S
6
) and then whether the clock skew exceeds the target value is checked again (S
3
, S
4
). The process ends if the step S
4
shows that the clock skew has become equal to or smaller than the target value. In this way, the conventional technique adjusts the clock skew through replacements between driver elements having different driving capabilities and different input capacitances.
In the conventional technique, since a driver element is replaced by another driver element having a different input capacitance, the circuit characteristic varies seen from the preceding circuit. As a result, the replacement of the driver elements may require correction of the preceding circuit. Furthermore, the driver elements are generally exchanged between elements having their input pins and output pins laid out in different positions, so that replacing the driver elements requires correction of the interconnections. Thus, the placement and routing may have to be largely corrected every time a driver element is replaced, which increases the time required for the design. Moreover, correcting the placement and routing changes factors contributing to the clock skew, which makes it difficult to precisely adjust the clock skew.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described problems of the conventional technique, and an object of the present invention is to obtain a placement and routing method for a clock distribution circuit, a clock distribution circuit manufacturing method, a semiconductor device manufacturing method, a clock distribution circuit and a semiconductor device which allow the clock skew to be adjusted highly precisely and easily.
A first aspect of the present invention is directed to a placement and routing method for a clock distribution circuit which receives a clock and supplies the clock to a load circuit. According to the first aspect, the method comprises the steps of: (a) temporarily placing and routing a group of elements having a common input capacitance to form the clock distribution circuit; and (b) until an evaluated value of clock skew becomes equal to or smaller than a target value, making a selective replacement of an element belonging to the group of elements among a plurality of elements having a common input capacitance and selected from a group consisting of a plurality of driver elements having different driving capabilities, a driver element having an opened output pin and a capacitance element interposed between an input pin and a stable potential line.
Preferably, according to a second aspect, in the placement and routing method for a clock distribution circuit, the step (b) makes the selective replacement of an element belonging to the group of elements between a first driver element and a second driver element identical to the first driver element and having an opened output pin until the evaluated value of clock skew becomes equal to or smaller than the target value.
Preferably, according to a third aspect, in the placement and routing method for a clock distribution circuit, the step (b) makes the selective replacement of an element belonging to the element group between a driver element and a capacitance element sharing a common input capacitance with the driver element and interposed between an input pin and a stable potential line until the evaluated value of clock skew becomes equal to or smaller than the target value.
Preferably, according to a fourth aspect, in the placement and routing method for a clock distribution circuit, the step (b) makes the selective replacement of an element belonging to the element group among a plurality of driver elements having different driving capabilities and a c
Browne Lynne H.
Patel Nitin C.
Renesas Technology Corp.
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