Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2006-08-01
2006-08-01
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C709S232000, C709S238000, C709S248000, C370S441000, C370S503000
Reexamination Certificate
active
07085950
ABSTRACT:
A high-speed parallel data communication approach overcomes data skewing concerns by concurrently transmitting data in a plurality of multiple-bit groups and, after receiving the concurrently-transmitted data, realigning skew-caused misalignments between the groups. In one particular example embodiment, for each group, an arrangement transfers the data in parallel and along with a clock signal for synchronizing digital data. The transferred digital data is synchronously collected via the clock signal for the group. At the receiving module, the data collected for each group is aligned using each group's dedicated clock signal. Skew across clock-domain groups is tolerated and overcome by processing the data and the skew first within each clock domain group, and then between groups.
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1990-245433/TP79010, Jul. 1990, Derwent.
Ehmann Gregory E.
Pontius Timothy
Sessions D. C.
Koninklijke Philips Electronics , N.V.
Perveen Rehana
Ure Michael J.
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