Method, apparatus, and system for high speed data transfer...

Details Method, apparatus, and system for high speed data transfer... Method, apparatus, and system for high speed data transfer...

2005-02-01

2005-02-01

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S401000, C713S500000

Reexamination Certificate

active

06851069

ABSTRACT:
According to one aspect of the invention, a method is provided in which a first clock signal is generated. A second clock signal is derived from the first clock signal. The second clock signal is delayed relative to the first clock signal by a first delay period by a delay locked loop (DLL) circuit. The second clock signal is used to latch incoming data from a memory device.

REFERENCES:
patent: 6363465 (2002-03-01), Toda

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