High-throughput interface between a system memory controller...

Holding mechanism for changing operation modes in a pipelined co

Hub/router for communication between cores using cartesian...

Hybrid branch prediction device with two levels of branch...

Hybrid branch prediction using a global selection counter...

Hybrid branch predictor having negative ovedrride signals

Hybrid branch predictor with improved selector table update...

Hybrid hypercube/torus architecture

Hypercomputer

Hypercomputer

I/O protocol for highly configurable multi-node processing syste

IBM PC compatible multi-chip module

IBM PC compatible multi-chip module

IC comprising network of microprocessors communicating data...

IC containing matrices of plural type operation units with...

IC with wait state registers

IC with wait state registers

Identification and correction of cyclically recurring errors...

Identification bit at a predetermined instruction location...

Identifying and processing essential and non-essential code...