Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-02-01
2009-08-18
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S015000
Reexamination Certificate
active
07577821
ABSTRACT:
An integrated circuit device comprising a data processing block including a first matrix and a second matrix is disclosed. The first matrix and the second matrix respectively include a plurality of types of operation units and a wiring group for connecting the plurality of types of operation units, a configuration of data flow with the plurality of types of operation units being changeable by changing a route of the wiring group for data supplying to the plurality of types of operation units. One of the plurality of types of operation units is a delay type operation unit that include a data path suited to processing for delaying a transfer time of data. The wiring group of the first matrix and the wiring group of the second matrix are separated, and the integrated circuit device further comprises a plurality of the delay type operation units that are arranged along boundary of the first matrix and the second matrix for connecting the wiring group of the first matrix and the wiring group of the second matrix via data paths included in the plurality of the delay type operation units.
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Ikeda Kenji
Sato Tomoyoshi
Shimura Hiroshi
IPFlex Inc.
Kim Kenneth S
Marshall & Gerstein & Borun LLP
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