Stream processing system having a reconfigurable memory module

Streaming vector processor with reconfigurable...

Structure for a single shared instruction predecoder for...

Structure for dynamically adjusting pipelined data paths for...

Structure of processor having a plurality of main processors and

Structured programming control flow in a SIMD architecture

Structured programming control flow using a disable mask in...

Sub-pipelined and pipelined execution in a VLIW

Substitute register for use in a high speed data processor

Substituting specified instruction with NOP to functional...

Subsystem bridge of AMBA's ASB bus to peripheral...

Super-reconfigurable fabric architecture (SURFA): a...

Superscalar instruction decoder including an instruction queue

Superscalar microprocessor configured to predict return addresse

Superscalar microprocessor configured to predict return...

Superscalar microprocessor employing a future file for storing r

Superscalar microprocessor for out-of-order and concurrently exe

Superscalar microprocessor having multi-pipe dispatch and...

Superscalar microprocessor including a high speed instruction al

Superscalar microprocessor including a load/store unit,...