Superscalar instruction decoder including an instruction queue

Details Superscalar instruction decoder including an instruction queue Superscalar instruction decoder including an instruction queue

1997-08-05

2001-02-13

Vu, Viet D. (Department: 2758)

Electrical computers and digital processing systems: processing

Instruction decoding

C712S209000, C712S212000, C712S215000

Reexamination Certificate

active

06189087

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to microprocessor architecture, and more particularly to superscalar instruction decoder architecture.
2. Description of Related Art
General purpose processors typically are based on scalar instruction sets. Processor architectures are either RISC (Reduced Instruction Set Computer) -based or CISC (Complex Instruction Set Computer) -based. Each approach has its advantages and disadvantages, as has been widely discussed in the literature.
The term “superscalar” describes a computer implementation that improves performance by concurrent execution of scalar instructions. Progress in implementing superscalar RISC architectures has been good. Scalar RISC architectures typically are defined with a pipelined implementation in mind, and include many features which facilitate superscalar implementation. These features include a fixed format and fixed length instructions, explicit instruction operands, and a load/store architecture. Superscalar RISC architectures are described in Johnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, N.J., 1991, which is incorporated herein by reference in its entirety.
Although interest has been expressed in achieving superscalar CISC architectures, progress has been hindered in part because few CISC architectures were defined with superscalar implementation in mind. CISC architectures were defined at a time when the principal implementation technique was microcode interpretation of the instruction set, with an emphasis on deciding which operations should be combined into instructions rather than designing operations so that they could be overlapped. While enormously versatile, microcode interpretation does not facilitate development of pipelined architectures or superscalar architectures. Difficulties arise from numerous aspects of conventional CISC architectures, including instruction format complexity, frequent register reuse, frequent memory access, and the inclusion of unusually complex instructions.
An example of a CISC instruction format is the instruction format of the Intel i486™ microprocessor, which is available from Intel Corporation of Santa Clara, Calif. In this instruction format, an instruction may have an operation code (“opcode”) consisting of one or two opcode bytes, a modify register or memory (“mod r/m”) byte, a scale-index-base (“sib”) byte, displacement bytes, and immediate date bytes. The opcode specifies the operation code, and may also contain a register identifier. The mod r/m byte specifies whether an operand is in a register or in memory. If the operand is in memory, fields in the mod r/m byte specify the addressing mode to be used. Certain encodings of the mod r/m byte indicate that a second byte, the sib byte, follows to fully specify the addressing mode. The sib byte consists of a 2-bit scale field, a 3-bit index field, and a 3-bit base field. These fields are used in complex memory addressing modes to specify how address computation is done. The displacement byte is used in address computation. The immediate data byte is used for an instruction operand. One or more additional bytes, known as prefix bytes, may appear before the opcode byte. The prefix byte changes the interpretation of the instruction, adding additional complexity. The length of the instruction can vary as well. The mninimum instruction consists of a single opcode byte and is 8 bits long. A long instruction that includes a prefix byte may be 104 bits long. Longer instructions containing more than a single prefix byte are possible as well.
An example of a recent microprocessor having a CISC superscalar architecture is the Pentium™ microprocessor, available form Intel Corporation of Santa Clara, Calif. The improved performance of the Pentium microprocessor relative to the i486 microprocessor is due in part to its superscalar architecture. Unfortunately, even new superscalar CISC architectures such as the Pentium microprocessor remain limited by various aspects of conventional CISC architectures, including instruction format complexity, frequent register reuse, frequent memory access, and the inclusion of unusually complex instructions.
SUMMARY OF THE INVENTION
Improved processor performance is facilitated by the present invention, which in one embodiment is a method for instruction decoding in which the CISC opcodes and addressing information of CISC instructions which map to respective numbers of RISC-like operations (ROPs) are identified and aligned into dispatch positions based on the number of ROPs to which the instructions map. ROP opcodes and addressing information are decoded from the CISC opcodes and addressing information based on, for each CISC instruction, the position of a dispatch position decoding the CISC instruction relative to other dispatch positions decoding the same CISC instruction. The ROP opcode and addressing information from the dispatch positions is driven in parallel to a RISC core.
Other embodiments of the invention include means for carrying out the foregoing method.
Another embodiment of the invention is an apparatus for dispatching up to a plurality “m” of ROPs in parallel, wherein the ROPs are mapped from one or more CISC instructions. The apparatus includes a memory for storing a CISC instruction and pre-decode information, which includes a value identifying the number of ROPs to which the CISC instruction maps. A multiplexer having a plurality “m” of outputs is coupled to the memory for directing information from the CISC instruction to unallocated ones of the multiplexer outputs equal to the number of ROPs to which the CISC instruction maps, up to “m” ROPs. A plurality of conversion paths are respectively coupled to the multiplexer outputs for converting the CISC instruction information into respective ROPs to which the CISC instruction maps. Dispatch logic is coupled to the conversion paths for dispatching the ROPs in a current dispatch window.
In another embodiment, the simple and common CISC instructions are encoded into one to three ROP sequences of primitive ROPs, which are then dispatched in parallel. The encoding is done for each dispatch position in a “fastpath,” which decodes a CISC instruction into an ROP and dispatches it to the RISC core. The fastpath uses pre-decoded information accompanying each CISC instruction byte to determine where instruction boundaries are and the number of ROPs for each CISC instruction.
In another embodiment, complicated instructions, ie., those requiring four or more ROPs, and infrequently used instructions are encoded using an entrypoint into microcode ROM. At the entrypoint, no additional CISC instructions are issued, so that the full issue width is available for the complex instruction. The ROPs from microcode ROM are dispatched from the four dispatch positions.


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