Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
1998-08-18
2001-07-10
Ellis, Richard L. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S221000
Reexamination Certificate
active
06260136
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processor comprising a register file and a plurality of operational units.
With recent advances in LSI technology, a high-performance digital signal processor has been implemented on a single chip to perform complicated data processing including addition, subtraction, and multiplication. In such a field of application as mobile telephone, high-speed data processing is particularly needed to perform compression/decompression of a large amount of information.
A known example of a high-speed data processor uses a pipeline control system, which comprises a small-capacity and high-speed register file in addition to a large-capacity memory such as a SRAM (static random access memory) and a low-speed memory such as a ROM (read-only memory). The pipeline data processor is composed of the register file having a plurality of general-purpose registers each for storing data and a plurality of operational units including an arithmetic and logic unit and a multiplier unit, which are connected to each other via buses. In the pipeline data processor, the high-speed register file is used to store data for operation. For example, the arithmetic and logic unit receives two operands from the register file and performs the addition of the two operands in response to an addition instruction. Data representing the result of the addition is written in a designated one of the general-purpose registers in the resister file. The multiplier unit receives two operands from the register file and performs the multiplication of the two operands in response to a multiplication instruction. Data representing the result of the multiplication is written in a designated one of the general-purpose registers in the register file.
In general, a multiplication process requires a longer time than an addition/subtraction process. Therefore, the multiplier unit forms a critical path in a conventional pipeline data processor so that the upper-limit frequency of a pipeline clock is determined by the multiplier unit. Besides, the time required to write the result of the operation performed by the multiplier unit in the register file via a bus is not negligible because it causes a serious delay in data transfer via the bus forming a long path.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to improve the operational speed of a data processor comprising a register file and a plurality of operational units.
To attain the object, the present invention provides a substitute register for storing data representing the result of operation performed by a specified one of the plurality of operational units (e.g., multiplier unit) in place of any of a plurality of general-purpose registers in the register file, which is disposed in the vicinity of the specific operational unit. The arrangement saves time required to write the data representing the result of the operation performed by the specific operational unit in the register file via a bus. The general-purpose register in place of which the substitute register stores the data representing the result of the operation performed by the specific operational unit is indicated by a tag stored in a tag register. When an instruction accompanied by a read address for specifying from which one of the general-purpose registers data should be read is given and the read address coincides with the tag of the tag register, the data stored in the substitute register is read therefrom.
REFERENCES:
patent: 5126964 (1992-06-01), Zurawski
patent: 5260897 (1993-11-01), Toriumi et al.
patent: 5954811 (1999-09-01), Garde
patent: 5987597 (1999-11-01), Miura et al.
patent: 6026421 (2000-02-01), Sabin et al.
Ellis Richard L.
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Robinson Eric J.
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