Superscalar microprocessor having multi-pipe dispatch and...

Electrical computers and digital processing systems: processing – Instruction issuing

Reexamination Certificate

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Reexamination Certificate

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07082517

ABSTRACT:
In a computer system for use as a symetrical multiprocessor, a superscalar microprocessor apparatus allows dispatching and executing multi-cycle and complex instructions Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). Multiple execution pipes correspond to the instruction dispatch ports and the execution unit is a Fixed Point Unit (FXU) which contains three execution dataflow pipes (X, Y and Z) and one control pipe (R). The FXU logic then execute these instructions on the available FXU pipes. This results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.

REFERENCES:
patent: 4766566 (1988-08-01), Chuang
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 5155817 (1992-10-01), Kishigami et al.
patent: 5530825 (1996-06-01), Black et al.
Schwarz, E. M. et al. “The microarchitecture of the IBM eServer z900 processor.” IBM J. Res. & Dev. IBM: 2002.

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