Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Reexamination Certificate
2011-08-16
2011-08-16
Fennema, Robert (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
Reexamination Certificate
active
08001361
ABSTRACT:
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for improved techniques for executing instructions in a pipelined manner is provided. Such techniques may reduce stalls that occur when executing dependent instructions. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.
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Fennema Robert
International Business Machines - Corporation
Patterson & Sheridan LLP
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