Stream processing system having a reconfigurable memory module

Details Stream processing system having a reconfigurable memory module Stream processing system having a reconfigurable memory module

2009-05-05

2011-12-27

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S010000

Reexamination Certificate

active

08086824

ABSTRACT:
A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module. The stream processing module includes a number (N) of stream processing units, and the memory module is configured with a number (N) of memory bank units each corresponding to a respective one of the stream processing units. The memory module is reconfigurable based on a desired inter-level configuration so that each of the memory bank units is configured to have a memory size sufficient to meet processing requirement of the respective one of the stream processing units.

REFERENCES:
Suh et al.; Dynamic Cache Partitioning for Simultaneous Multithreading Systems; Aug. 2001.
Iyer et al.; QoS Policies and Architecture for Cache/Memory in CMP Platforms; 2007.
Kim et al.; Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture; 2004.

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