Simultaneous multi-thread instructions issue to execution...

Simultaneous parity generating/reading circuit for massively par

Simultaneous speculative threading light mode

Simultaneously assigning corresponding entry in multiple...

Simultaneously setting prefetch address and fetch address...

Single array banked branch target buffer

Single array banked branch target buffer

Single chip microcomputer having a dedicated address bus and...

Single chip multiprocessor with shared execution units

Single cycle context switching by swapping a primary latch...

Single cycle context switching by swapping a primary latch...

Single cycle transition pipeline processing using shadow...

Single instruction having op code and stack control field

Single instruction method of seizing control of program executio

Single instruction multiple data array cell

Single instruction multiple data massively parallel...

Single instruction multiple data processing allowing the...

Single instruction stream multiple data stream processor

Single integrated circuit embodying a dual heterogenous...

Single operation per-bit memory access