Single array banked branch target buffer

Details Single array banked branch target buffer Single array banked branch target buffer

2006-05-16

2006-05-16

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S239000

Reexamination Certificate

active

07047400

ABSTRACT:
An Instruction Pointer (IP) signal is received comprising an IP tag field and an IP set field. A plurality of entries corresponding to the IP set field are read, each of the entries comprising an entry tag, an entry bank, and entry data. Each entry tag and entry bank is then compared with the IP tag and each of the plurality of banks. In one embodiment, the IP tag is concatenated with a number representing one of the plurality of banks and compared to the entry tag and entry bank. Separate comparisons may then be performed for each of the other banks.

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