Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching
Reexamination Certificate
2005-11-15
2005-11-15
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction fetching
Prefetching
C711S213000, C712S205000, C712S237000, C712S240000
Reexamination Certificate
active
06965983
ABSTRACT:
A pipelined CPU includes a pre-fetch (PF) stage for performing branch prediction, and an instruction fetch (IF) stage for fetching instructions that are to be later processed by an execution (EX) stage. The PF stage has a PF address (PFA) register for storing the address of an instruction being processed by the PF stage, and the IF stage has an IF address (IFA) register for storing the address of an instruction to be fetched for later execution. The CPU also includes address register control (ARC) circuitry for setting the contents of the PFA and the IFA. The ARC accepts branch-prediction results from the PF stage to determine the subsequent contents of the PFA and the IFA. If the PF stage predicts a branch, then the ARC sets the next address of the PFA to be sequentially after a predicted branch address, and simultaneously sets the next address of the IFA to be the predicted branch address.
REFERENCES:
patent: 4943908 (1990-07-01), Emma et al.
patent: 5237666 (1993-08-01), Suzuki et al.
patent: 5642500 (1997-06-01), Inoue
patent: 2001/0027515 (2001-10-01), Ukai et al.
Faraday Technology Corp.
Hsu Winston
Kim Kenneth S.
LandOfFree
Simultaneously setting prefetch address and fetch address... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simultaneously setting prefetch address and fetch address..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simultaneously setting prefetch address and fetch address... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3514408