Simultaneously setting prefetch address and fetch address...

Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching

Reexamination Certificate

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Details

C711S213000, C712S205000, C712S237000, C712S240000

Reexamination Certificate

active

06965983

ABSTRACT:
A pipelined CPU includes a pre-fetch (PF) stage for performing branch prediction, and an instruction fetch (IF) stage for fetching instructions that are to be later processed by an execution (EX) stage. The PF stage has a PF address (PFA) register for storing the address of an instruction being processed by the PF stage, and the IF stage has an IF address (IFA) register for storing the address of an instruction to be fetched for later execution. The CPU also includes address register control (ARC) circuitry for setting the contents of the PFA and the IFA. The ARC accepts branch-prediction results from the PF stage to determine the subsequent contents of the PFA and the IFA. If the PF stage predicts a branch, then the ARC sets the next address of the PFA to be sequentially after a predicted branch address, and simultaneously sets the next address of the IFA to be the predicted branch address.

REFERENCES:
patent: 4943908 (1990-07-01), Emma et al.
patent: 5237666 (1993-08-01), Suzuki et al.
patent: 5642500 (1997-06-01), Inoue
patent: 2001/0027515 (2001-10-01), Ukai et al.

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