Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
1995-06-07
2001-04-24
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S033000, C710S120000
Reexamination Certificate
active
06223279
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a single chip microcomputer, and particularly to a high-speed single chip microcomputer which is compact and has a register bank function to form a high-performance system.
2. Description of the Prior Art
General purpose microcomputers (MCUs) and microprocessors (MPUs) used for built-in control devices usually employ a register bank function to process interrupts at high speed or to deal with multitasking and multiprogramming systems.
The MCUs and MPUs usually incorporate a set of general purpose registers (for example, eight 16-bit registers), a program counter, and a processor status word. These registers are selected by a user program and used for holding various data such as operation results and program statuses.
When an interrupt occurs to execute an interrupt processing program, or when a request (task switch) for executing an urgent program arises under a multitask environment, or when a subroutine call occurs for shifting control from a main program to a subroutine program during the execution of a program, the MCUs and MPUs temporarily suspend the presently executing program and start a different program. At this time, data held in the registers must be temporarily saved in another location (usually, an external memory), and data necessary for the different program must be newly read from the outside and set in the registers.
After the different program is completed, the saved data must be restored in the registers to resume the suspended program.
If the MCUs and MPUs have no register bank function, the contents of the registers must be saved in the external memory, or in a RAM in the case of single chip MCUs. Generally, the external memory is accessible only at low speed, so that it takes a very long time for saving and restoring data of the registers to and from the external memory. This is a bottleneck for the built-in control devices that must quickly respond to an interrupt request in real time, and lowers system performance.
To solve the problem and improve system performance, the MCUs and MPUs often employ the register bank function. The register bank function involves several sets of general purpose registers which are built in the processor. Each set comprises, for example, sixteen 16-bit general purpose registers. If the register bank function uses eight register banks, eight sets of general purpose registers, i.e., 128(8×16) 16-bit general purpose registers must be prepared.
These general purpose register sets (register banks) are properly switched from one to another when an interrupt or a task switch occurs, to shorten an interrupt response time or a task switching time and improve system performance. When it is necessary to save and restore the contents of one general purpose register set due to an interrupt or a task switch, the register bank function is very useful to eliminate saving the contents of the general purpose register set into the external memory at slow speed and slowly restoring the data from the external memory. The register bank function internally switches the general purpose register sets from one to another at high speed without using the slow-speed external memory. Thus, the register bank function improves a register bank switching speed and shortens an interrupt and task switch handling time.
FIG. 1
shows a single chip microcomputer employing the conventional register bank function, and
FIG. 2
shows a CPU core disposed in the single chip microcomputer.
In
FIG. 1
, the single chip microcomputer
100
comprises the CPU core
101
, a on-chip RAM
103
, a on-chip ROM
105
, a bus controller
107
, an interrupt controller
109
, a timer
111
, a serial I/O
113
, etc. These elements send and receive data through a system bus SYSBUS (including an address bus ABUS and a data bus DBUS) in the chip. Data communication with the outside of the chip is carried out through the bus controller
107
and an I/O pad.
In
FIG. 2
, the CPU core
101
incorporates a plurality of general purpose register sets RF
1
through RF
8
forming register banks. These register sets are connected to a plurality of internal data buses IDBUS
1
through IDBUS
3
in the CPU core
101
, so that data are transferred and processed between the register sets RF
1
to RF
8
and an ALU (arithmetic and logic unit)
125
, etc.
It is important for efficiently processing data in the CPU core
101
that the register sets RF
1
to RF
8
are accessible from a plurality of the data buses IDBUS
1
to IDBUS
3
. Generally, the number of ports of a memory that forms the register sets is at least three, i.e., two for reading and one for writing. When another writing port is added to provide four ports in total, data processing efficiency will be improved. Accordingly, the register sets are usually formed from a RAM having three or four ports.
The CPU core
101
also includes a bank specifying register
127
for specifying one register bank (general purpose register set) to use, a processor status word
128
for storing the statuses of the CPU, and a program counter
129
for storing the address of a program presently executed. The bank specifying register
127
holds the number of the register bank presently used for executing the program, i.e., the register
127
represents which bank is currently used. Switching the register banks from one to another is carried out by rewriting the bank specifying register
127
. After the present program is suspended and the bank specifying register
127
is rewritten, the general purpose register set corresponding to the newly specified number starts to be used. From this moment, the previously used register set will not be used. The contents of the previously used register set, however, will be preserved.
When an interrupt occurs, the contents of a general purpose register set are saved as follows:
(1) The contents of the processor status word, program counter, and bank specifying register are saved into an external memory (stack) through the system bus.
(2) The bank specifying register is updated to specify another general purpose register set to be used.
Once the interrupt process is completed, the original program is resumed in the following manner:
(1) The previously saved data of the program counter, pr
1
ocessor status word, and bank specifying register are restored from the external memory through the system bus.
This method eliminates the need to save and restore the contents of the general purpose register set to and from the external memory through the system bus at slow speed, and instead, enables the general purpose register sets in the CPU to be switched from one to another at high speed.
In these days, requirements for functions of the MCUs and MPUs for built-in control devices are increasing. As a result, the number of register banks is increasing from around 4 to 8 banks to 16, 32, 64, and even 256 banks. As the number of the register banks increases, the conventional register bank method has raised the following problems.
In designing a multiport memory, a space or silicon area occupied by a unit memory cell increases in proportion to the number of ports of the memory because the number of transistors and wiring increase in proportion to the number of the ports. Namely, the multiport general purpose register set inevitably needs a large space.
If the number of banks is around four, the silicon area problem is not too severe even if the bank involves large memory cells, because the total number of memory bits needed is not so large (if the size of each general purpose register set is 16 bits×16 registers, 1024 bits in total for four banks). In this case, the multiport memory does not cause serious trouble in terms of the die area.
When the number of the banks increases, the number of bits of each memory cell proportionally increases, and the area of the multiport memory no longer becomes ignorable. In addition, the multiport memory involving a large number of bits is difficult to design, consumes a lot of power, and operates at sl
Kanuma Akira
Nishimura Akira
Ogawa Sunao
Yamada Yasuo
Donaghue Larry D.
Foley & Lardner
Kabushiki Kaisha Toshiba
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