Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-09-06
2005-09-06
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
06941446
ABSTRACT:
A single instruction multiple data (SIMD) array cell for processing a data stream, the array including a plurality of cells, each cell having a memory circuit for storing a predetermined region of the data stream; a location register circuit for representing the size and location of the predetermined region of the data stream; a unique identification number; and an arithmetic logic unit responsive to the identification number and a single command common to all cells in a load mode to compute a unique start position for its cell for receiving the predetermined region of the direct memory access data stream. In an execution mode the command word includes an address field applicable to all cells, a data field and an instruction to be performed by the arithmetic logic unit. The arithmetic logic unit in each cell performs the instruction directly on the local value at that address in its memory with the data in the data field.
REFERENCES:
patent: 3805037 (1974-04-01), Ellison
patent: 4722050 (1988-01-01), Lee et al.
patent: 4847801 (1989-07-01), Tong
patent: 4852098 (1989-07-01), Brechard et al.
patent: 4918638 (1990-04-01), Matsumoto et al.
patent: 5095525 (1992-03-01), Almgren et al.
patent: 5182746 (1993-01-01), Hurlbut et al.
patent: 5214763 (1993-05-01), Blaner et al.
patent: 5379243 (1995-01-01), Greenberger et al.
patent: 5446850 (1995-08-01), Jeremiah et al.
patent: 5577262 (1996-11-01), Pechanek et al.
patent: 5689452 (1997-11-01), Cameron
patent: 5708836 (1998-01-01), Wilkinson et al.
patent: 5752068 (1998-05-01), Gilbert
patent: 5872988 (1999-02-01), Duranton
patent: 6049815 (2000-04-01), Lambert et al.
patent: 6199086 (2001-03-01), Dworkin et al.
patent: 6199087 (2001-03-01), Blake et al.
patent: 6230179 (2001-05-01), Dworkin et al.
patent: 6246768 (2001-06-01), Kim
patent: 6317819 (2001-11-01), Morton
patent: 6349318 (2002-02-01), Vanstone et al.
patent: 6434662 (2002-08-01), Greene et al.
patent: 6581152 (2003-06-01), Barry et al.
patent: 6587864 (2003-07-01), Stein et al.
patent: 2002/0041685 (2002-04-01), McLoone et al.
patent: 2002/0147825 (2002-10-01), Stein et al.
patent: 2002/0174318 (2002-11-01), Stuttard et al.
patent: 2003/0103626 (2003-06-01), Stein et al.
patent: 2003/0105791 (2003-06-01), Stein et al.
patent: 2003/0110196 (2003-06-01), Stein et al.
patent: 2003/0115234 (2003-06-01), Stein et al.
patent: 2003/0133568 (2003-07-01), Stein et al.
patent: 2003/0140211 (2003-07-01), Stein et al.
patent: 2003/0140213 (2003-07-01), Stein et al.
patent: 2003/0149857 (2003-08-01), Stein et al.
patent: 1 246 389 (2002-10-01), None
Viktor Fischer,Realization of the Round 2 AES Candidates Using Altera FPGA, (Jan. 26, 2001) <http://csrc.nist.gov/CryptoToolkit/aes/roun2/conf3/papers/24-vfischer.pdf> (Micronic—Kosice, Slovakia).
Máire McLoone and J.V. McCanny,High Performance Single-Chip FPGA Rijndael Algorithm Implementations, CHES 2001 PROC, LNCS 2162, 65-76 (C.K. Koç et al. eds. May 16, 2001).
Elixent,Changing the Electronic Landscape(2001) <http://www.elixent.com> (elixent—Bristol, UK).
Elixent Application NoteJPEG Codec(Dec. 9, 2002) <http://www.elixent.com/assets/jpeg-coder.pdf> (elixent—Bristol, UK).
U.S. Appl. No. 10/440,330, filed May 16, 2003, Stein et al.
U.S. Appl. No. 10/395,620, filed Mar. 24, 2003, Stein et al.
V. Baumgarte et al.,PACT XPP—A Self-Reconfigurable Data Processing Architecture(Jun. 2001) <http://www.pactcorp.com/xneu/download/ersa01.pdf> (PACT XPP—Santa Clara, CA).
PACT Informationstechnologie GmbH,The XPP White Paper Release 2.1(Mar. 27, 2002) <http://www.pactcorp.com/xneu/download/xpp_white_paper.pdf> (PACT XPP—Santa Clara, CA).
Kablotsky Joshua A.
Stein Yosef
Analog Devices Inc.
Iandiorio & Teska
Treat William M.
LandOfFree
Single instruction multiple data array cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Single instruction multiple data array cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single instruction multiple data array cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3403879