Non-aligned double word fetch buffer

Details Non-aligned double word fetch buffer Non-aligned double word fetch buffer

1998-08-07

2000-09-05

Follansbee, John A.

Electrical computers and digital processing systems: processing

Instruction alignment

712 2, 712 5, 712216, 712224, G06F 1500

Patent

active

061158054

ABSTRACT:
A non-aligned double word fetch buffer is integrated into a digital signal processor to handle non-aligned double word (32 bit) fetches. When a misaligned double word fetch is detected, the buffer causes a two cycle non-interruptable instruction to be initiated. The first cycle is a 16-bit misaligned data fetch. The address pointer is incremented by 2 and stored in a temporary pointer register. The second cycle is a 32-bit double word fetch based on the temporary pointer with its least significant bit set to 0 (an aligned fetch). The low word from this fetch is used to satisfy the current misaligned double word fetch and the high word is stored in a temporary buffer register in case it proves useful in subsequent misaligned double fetch instructions. Finally, the temporary address pointer is incremented by 2 for possible use in subsequent misaligned fetches. If a subsequent misaligned fetch using the same address pointer is detected, a one-cycle misaligned double word fetch may be simulated by using the buffered memory fetch data combined with another aligned double word fetch and an appropriate pointer update. A double word per cycle data rate may thereby be maintained during an entire sequence of misaligned data fetches, except when processing the first state of the loop, during which time the buffer is set up.

REFERENCES:
patent: 4777594 (1988-10-01), Jones et al.
patent: 5179671 (1993-01-01), Kelly et al.
patent: 5550972 (1996-08-01), Patrick et al.
patent: 5696946 (1997-12-01), Patrick et al.

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