Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2011-08-02
2011-08-02
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S209000
Reexamination Certificate
active
07991978
ABSTRACT:
Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, each of a plurality of the IP blocks including at least one computer processor, each such computer processor implementing a plurality of hardware threads of execution; low latency, high bandwidth application messaging interconnects; memory communications controllers; network interface controllers; and routers; each of the IP blocks adapted to a router through a separate one of the low latency, high bandwidth application messaging interconnects, a separate one of the memory communications controllers, and a separate one of the network interface controllers; each application messaging interconnect abstracting into an architected state of each processor, for manipulation by computer programs executing on the processor, hardware inter-thread communications among the hardware threads of execution; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers.
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Kuesel Jamie R.
Kupferschmidt Mark G.
Mejdrich Eric O.
Schardt Paul E.
Biggers & Ohanian LLP
Chan Eddie
Faherty Corey
International Business Machines - Corporation
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