Dependency tracking for enabling successive processor...

Design structure for single hot forward interconnect scheme...

Designating operands with fewer bits in instruction code by...

Detachable processor module containing external microcode expans

Detecting full conditions in a queue

Detecting long latency pipeline stalls for thread switching

Detecting memory-hazard conflicts during vector processing

Detecting raw hazards in an object-addressed memory...

Detecting self-modifying code in a pipelined processor with bran

Detection of data hazards between instructions by decoding...

Detection of overwrite modification by preceding instruction...

Determination of approaching instruction starvation of...

Determination of execution resource allocation based on...

Determining if a register is ready to exchange data with a...

Determining length of instruction with escape and addressing...

Determining length of instruction with multiple byte escape...

Determining register availability for register renaming

Determining successful completion of an instruction by...

Determining target addresses for instruction flow changing...

Determining thermal characteristics of instruction sets