Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
2000-03-21
2003-05-27
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction fetching
C711S141000, C711S146000, C712S207000, C712S216000, C712S226000
Reexamination Certificate
active
06571329
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing apparatus for use in a pipeline process system, and more specifically to an information processing apparatus for detecting a possibility that the contents of the instructions subsequent to an instruction, for example, a store instruction, to write an instruction execution result to a main storage device can be overwritten by the instruction.
2. Description of the Related Art
In an information processing apparatus for use in a pipeline process system, a superscalar process system, an out-of-order process system, etc., instructions subsequent to an instruction can be sequentially fetched (or prefetched) before the completion of the execution of the instruction, put in a pipeline, and sequentially executed, thereby improving the performance of the entire operation.
Assume that an instruction has already been executed and its execution result is written to the main storage device, if the contents of an instruction to be overwritten are already prefetched and stored in, for example, an instruction buffer, then it is obvious that the instruction before the overwriting process is not to be executed, but the instruction after the overwriting process is to be executed. Thus, there is a possibility that the contents of an already fetched instruction are overwritten upon completion of a preceding store instruction. Therefore, it is necessary to control the execution of an instruction with the possibility for the overwrite of the instruction taken into account.
Whether or not the contents of an instruction should be overwritten should be determined before the completion of the execution of a store instruction to execute the overwriting process. Otherwise, if the store instruction is to overwrite an instruction immediately after the store instruction, there is a strong possibility that the instruction before the overwriting process can be erroneously executed. Therefore, a method of quickly determining the possibility for the overwrite of an instruction is either to shorten the determination time using a simple overwrite determination circuit, or to reserve the time taken to determine the possibility for the overwriting process by limiting the flow of an instruction pipeline when there is a store instruction to write an instruction execution result to the main storage device.
When the above described store instruction exists in the conventional technology, an instruction fetching operation is held until the execution result of the store instruction is determined, and a simple determination circuit is designed by controlling the length of an instruction sequence in an instruction pipeline to be equal to or shorter than a predetermined length, thereby shortening the time taken to determine the possibility for an overwriting process. However, since a store instruction is frequently used, each time the store instruction appears in an instruction sequence, the instruction pipeline stops, thereby considerably lowering the performance of the entire process.
SUMMARY OF THE INVENTION
The present invention aims at improving the performance of the process of an information processing apparatus which includes an instruction fetch port, and can detect the possibility for the overwrite of an instruction fetched from the instruction fetch port by correctly detecting the length of an instruction sequence already stored in an instruction buffer for storing an instruction to be fetched before the execution of instructions, and an instruction to be determined in the instructions being or already executed, and by correctly detecting the possibility for the overwrite of the contents of an instruction fetched from one instruction port.
The feature of the present invention is to include an information processing apparatus which has one or more instruction fetch ports for fetching an instruction, and detects the possibility for the overwrite of an instruction fetched from the instruction fetch port. The information processing apparatus includes an instruction fetch counter unit for counting the lengths of all instruction sequences containing instructions fetched from an instruction fetch port, containing the last fetched instruction, containing instructions fetched before the last fetched instruction, and containing instructions whose instruction addresses are in series with the address of the last fetched instruction; and an instruction overwrite possibility determination unit for detecting the possibility for an instruction overwriting process in which at least a part of the range of the addresses to be stored overlaps the addresses of the instructions in all instruction sequences, and at least a part of the instruction sequences is overwritten according to the address at a specified position in all instruction sequences, the storage target address at which the execution result of a completed store instruction is stored, and an output value of the instruction fetch counter unit.
With the information processing apparatus according to the present invention, it is possible to quickly determine the possibility for the overwrite of a subsequent instruction already fetched or executed when a storage target address at which an execution result of a store instruction is stored is determined, thereby requiring no limit of the flow of an instruction pipeline containing a store instruction. Accordingly, the performance of the information processing apparatus can be efficiently improved.
REFERENCES:
patent: 5721865 (1998-02-01), Shintani et al.
patent: 5742791 (1998-04-01), Mahalingaiah et al.
patent: 5826073 (1998-10-01), Ben-Meir et al.
patent: 5835949 (1998-11-01), Quattromani et al.
patent: 6009516 (1999-12-01), Steiss et al.
patent: 6237088 (2001-05-01), Zaidi
patent: 6405307 (2002-06-01), Murty et al.
patent: 6415360 (2002-07-01), Hughes et al.
patent: 63-311438 (1988-12-01), None
patent: 4-246728 (1992-09-01), None
patent: 8-194615 (1996-07-01), None
Inoue Aiichiro
Ukai Masaki
Fujitsu Limited
Kim Kenneth S.
Staas & Halsey , LLP
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