Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2011-06-21
2011-06-21
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S213000
Reexamination Certificate
active
07966476
ABSTRACT:
A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
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Binns Frank
Coke James S.
Jackson David B.
Naydenov Ves A.
Rodgers Scott D.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Kenneth S
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