Designating operands with fewer bits in instruction code by...

Electrical computers and digital processing systems: processing – Instruction decoding

Reexamination Certificate

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C712S210000

Reexamination Certificate

active

07814299

ABSTRACT:
A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.

REFERENCES:
patent: 5991870 (1999-11-01), Koumura et al.
patent: 6385714 (2002-05-01), Koumura et al.

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