Determining target addresses for instruction flow changing...

Electrical computers and digital processing systems: processing – Instruction fetching – Prefetching

Reexamination Certificate

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Reexamination Certificate

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07831806

ABSTRACT:
A data processing apparatus comprises a processor for executing a stream of instructions, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor for execution. The prefetch unit receives from the memory a plurality of prefetched instructions from sequential addresses in memory, and detects whether any prefetched instructions are an instruction flow changing instruction, and outputs a fetch address for a next instruction to be prefetched by the prefetch unit. Address generation logic is also provided which, for a selected prefetched instruction that is detected to be an instruction flow changing instruction, determines a target address to be output as the fetch address. Address generation logic has a first address generation path and a further generation path for determining the target address. The first address generation path generates the target address more quickly than the further address generation path.

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patent: 2003/0159019 (2003-08-01), Oldfield et al.
Hennessy, John. Patterson, David. “Computer Architecture: A Quantitative Approach”. Morgan Kaufmann Publishers Inc, Third Edition. May 17, 2002. pp. A-2 and A-3.
Furber, Steve. “ARM System-on-Chip Architecture”. Addison-Wesley, 2000. pp. 382-384, 387-388.

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