Detecting long latency pipeline stalls for thread switching

Details Detecting long latency pipeline stalls for thread switching Detecting long latency pipeline stalls for thread switching

1997-12-31

2000-01-18

Treat, William M.

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

712216, 712219, 712 23, 712 24, 712 42, 712228, G06F 938

Patent

active

060165421

ABSTRACT:
An apparatus is provided that operates in conjunction with a processor having registers and associated caches and a memory. A load management module monitors loads that return data to the registers, including bus requests generated in response to loads that miss in one or more of the caches. A cache miss register includes entries, each of which is associated with one of the registers. A mapping module maps a bus request to a register and sets a bit in a cache miss register entry associated with the register when the bus request is directed to a higher level structure in the memory system.

REFERENCES:
patent: 5535361 (1996-07-01), Hirata et al.
patent: 5761515 (1998-06-01), Barton, III et al.
patent: 5809450 (1998-09-01), Chrysos et al.
patent: 5839709 (1998-11-01), Larsen et al.
Loikkanen et al., "A Fine-Grain Multithreading Superscalar Architecture," Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, IEEE, pp. 163-168. Oct. 20-23, 1996.
Agarwal et al., "Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors," Micro, IEEE, vol. 13, Iss. 3, pp. 48-61, Jun. 1993.
Byrd et al., "Multithreaded Processor Architectures," Spectrum, IEEE, pp. 38-46, vol. 32, Iss. 8, Aug. 1995.
Bolychersky et al., "Dynamic Schedulling in RISC Processors Architectures," Proceedings on Computers and Digital Techniques, IEE, vol. 143, Iss. 5, pp. 309-317, Sep. 1996.
"Simultaneous Multithreading: A Platform for Next-Generation Processors", Eggers et al., Dept. of Computer Science and Engineering, Seattle, WA, pp. 1-15.
Compilation Issues for a Simultaneous Multithreading Processor Lo, et al., Dept. of Computer Science and Engineering, Seattle, WA, 2 pp.
"Converting Thread-Level Parallelism To Instruction-Level Parallelism Via Simultaneous Multithreading", Lo, et al., Dept. of Computer Science and Engineering, Seattle, WA, pp. 1-25
"Simultaneous Multithreadings: Maximizing On-Chip Parallelism", Tullsen, et al., Dept. of Computer Science and Engineering, Seattle, WA, pp. 1-12.
"Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", Tullsen, et al., Dept. of Computer Science and Engineering, Seattle, WA, pp. 1-12.
Increasing Superscalar Performance Through Multistreaming:, Yamamoto, et al., Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques, pp. 1-10.

Affiliated with

Also associated with

Rating

Detecting long latency pipeline stalls for thread switching does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Detecting long latency pipeline stalls for thread switching, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Detecting long latency pipeline stalls for thread switching will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-570386