Background completion of instruction and associated fetch reques

Details Background completion of instruction and associated fetch reques Background completion of instruction and associated fetch reques

1996-12-27

2000-07-11

Lee, Thomas C.

Electrical computers and digital processing systems: processing

Instruction fetching

712229, 712 23, 712 43, 711140, G06F 940, G06F 1576

Patent

active

060887885

ABSTRACT:
The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled. After the requested data returns from higher level memory, the storage control unit will dispatch the instruction from the first thread having received the cache miss to an unused slot in the storage pipeline. Consequently, this instruction from the first thread will be processed along with the instructions from the second thread.

REFERENCES:
patent: 5148536 (1992-09-01), Witek et al.
patent: 5197138 (1993-03-01), Hobbs et al.
patent: 5287508 (1994-02-01), Hejna, Jr. et al.
patent: 5361337 (1994-11-01), Okin
patent: 5404469 (1995-04-01), Chung et al.
patent: 5430850 (1995-07-01), Papadopoulos et al.
patent: 5471593 (1995-11-01), Branigin
Shuichi Sakai et al., "Reduced interprocessor-communication architecture and its implementation on EM-4", Parallel Computer, Elsevier Science B.V. pp. 754-769, Jan. 1994.
Manu Gulati et al., "Performance Study of a Multithreaded Superscalar Microprocessor", IEEE, pp. 291-301, 1996.
Douglas Donalson et al., "DISC: Dynamic Instruction Stream Computer An Evalutaion of Performance" IEEE, pp. 448-456, 1993.
Bernard Karl Gunther, "Superscalar Performance in a Multithreaded Microprocessor", University of Tasmania Hobart, Chapters 2 and 3, Dec. 1993.
Bradley J. Kish and Bruno R. Preiss, "Hobbes: A Multi-Threaded Superscalar Architecture", University of Waterloo, 1994.
Mike Johnson, "Superscalar Microprocessor Design", Prentice Hall, pp. 21, 46-47, 233-235, 268-272, 1991.
Howe's Free On-line Dictionary of Computing (http://www.instantweb.com/.about.foldoc/), background, foreground, Oct. 1994.
Song, Peter; Microprocessor Report, vol. 11, No. 9, pp. 13-18, "Multithreading Comes of Age".
Israel, Paul et al., 1995 Electronic Engineering Times (Jun. 19), pp. 78-80, "Chip set Aims to Speed Secondary Cache--Parallelism Enhances Level 2 Cache Runs".
Jouppi, Norman P., 17th Annual International Symposium on Computer Architecture (May 28-31, 1990), pp. 364-373, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers".
Stiliadis, Dimitrios et al, IEEE Proceedings of the 27th Annual Hawaii International Conference on System Sciences (1994), pp. 412-421, "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches".
Stiliadis, Dimitrios et al, IEEE Transactions on Computers, vol. 46, No. 5 (May 1997), pp. 603-610, "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches".
Wilson, Ron, Jul. 1, 1989 Computer Design, pp. 72-83, "Higher Speeds Push Embedded Systems to Multiprocessing".
Sporer, Michael et al, 33rd IEEE Computer Society International Conference, Feb. 29-Mar. 4, 1988 Spring Compcon, pp. 464-467, "An Introduction to the Architecture of the Stellar Graphics Supercomputer".
Lorin, Harold, John Wiley & Sons Publication, pp. 41-53, "Introduction to Computer Architecture and Organization".
Chang, Yen et al, Electronic Technology for Engineers and Engineering Managers, vol. 32, No. 8, Apr. 15, 1987, pp. 177-184, "Use Structured Arrays for High-Performance Data Processing".
Agarwal, Anant et al, IEEE Micro, vol. 13, No. 3, pp. 48-61, "Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors".
Laudon, James et al, Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, Oct. 4-7, 1994, "Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations".
Borkenhagen, John et al, Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 10-12, 1994, pp. 192-196, "AS/400 64-Bit PowerPC-Compatible Processor Implementation".
IBM Patent Application, Docket RO996-129, Filed Dec. 9, 1996, Serial No. 08/761,378, "Multi-Entry Fully Associative Transition Cache".
IBM Patent Application, Docket RO996-144, Filed Dec. 9, 1996, Serial No. 08/761,380, "Method and Apparatus for Prioritizing and Routing Commands from a Command Source to a Command Sink".
IBM Patent Application, Docket RO996-145, Filed Dec. 9, 1996, Serial No. 08/761,379, "Method and Apparatus for Tracking Processing of a Command".
"Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors," IEEE Micro, Agarwal et al., Jun. 1993, pp. 48-61.
"AS/400.TM. 64-bit PowerPC.TM.-Compatible Processor Implementation" Borkenhagen et al., Proceedings 1994 IEEE Int'l Conf. on Computer Design: VLSI in Computers and Processors, Oct. 10-12, 1994, pp. 192-196.
"Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations," presented at the Sixth Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, Laudon et al., pp. 308-318, Oct. 1994.

Affiliated with

Also associated with

Rating

Background completion of instruction and associated fetch reques does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Background completion of instruction and associated fetch reques, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Background completion of instruction and associated fetch reques will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-553027