Backing out of a processor architectural state

Details Backing out of a processor architectural state Backing out of a processor architectural state

1998-08-11

2002-06-25

Eng, David Y. (Department: 2155)

Electrical computers and digital processing systems: processing

Processing control

Processing sequence control

Reexamination Certificate

active

06412067

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computers and processors, and more specifically, to delaying the deallocation of registers and backing out of architectural states.
2. Description of the Related Art
Processors fetch and execute a sequence of instructions from memory. The instructions ordinarily manipulate data stored in memory or registers. Typically, the processor decodes the instructions into first and second types of micro-instructions adapted to execute on particular types of hardware units. The first type of micro-instruction loads and stores data between the memory and registers, which are typically internal to the processor. The second type of micro-instruction manipulates data stored in the internal registers and writes the results from the manipulations back to the internal registers. Since the number of internal registers is limited, an absence of available internal registers may occur causing a bottleneck at the decode stage. The processor ordinarily employs methods that efficiently use the internal registers to reduce the occurrence of decode bottlenecks.
One mechanism for using the limited number of internal registers entails producing instructions through several operations. First, the processor decodes an incoming instruction into one or more instructions having logical operands. Hereafter, logical operands are defined to mean dummy variables for some source and destination addresses of instructions. Second, an allocator assigns one or more of the available internal registers to the logical operands introduced in the first step. Third, a retirement unit deallocates the previously assigned internal registers of executed instructions without substantial delay when other instructions no longer need to read the contents of the registers. Deallocation makes more internal registers available for assignment to newly decoded instructions. Thus, retirement units should rapidly deallocate registers to reduce the occurrence of instruction decode bottlenecks.
Processors also have hardware for recovering from what are referred to as execution “exceptions”. Exceptions may be attributable to interrupts and faults generated during execution of instructions. Recovering from an exception involves both detecting the exception and reporting the exception to hardware that may re-execute any improperly executed instructions. The proper re-execution nominally involves returning the processor to a pre-exception state. Thus, re-execution may include restoring original data to internal registers and reinserting the excepting instruction and the instructions dependent thereupon back into execution pipelines.
A system designed to detect and report all exceptions may employ substantial hardware, i.e., a large area on the processor chip, and may encumber the ordinary retirement cycle. The detection of complex fault events may entail heavy area and time costs, because more verifications are ordinarily employed to check for complex faults. Complex fault detection may slow the retirement process with verifications for rarely occurring faults.
For a macro-instruction, I
1
, decoding into a sequence &mgr;I
1
, &mgr;I
2
, etc., an exception may occur on both the earlier and later members of the sequence, e.g., &mgr;I
1
, or &mgr;I
2
. Two methods may be pursued to recover from an exception on a later member, e.g., &mgr;I
2
. First, the processor may correct the condition causing the exception and re-execute only the excepting instructions by (a) detecting which instruction excepted, and (b) reinstating the initial execution state associated therewith. Second, the processor may correct the condition causing the exception and re-execute the entire sequence, i.e., &mgr;I′
1
, &mgr;I′
2
, etc., whenever any member of the sequence registers an exception. Implementing either of the above methods may be problematic.
Since detecting exceptions on individual members of a sequence may be complex, re-executing the entire sequence from decoding the macro-instruction may save time and reduce hardware needs. But, the sequence from the macro-instruction may include “retired” instructions, because earlier members, e.g., &mgr;
1
, may have completed execution. For example, the instruction R+R′→R destroys the original data in R when the instruction is retired, i.e., the architectural state has changed. Thus, executing earlier members of the sequence, e.g., &mgr;I
1
, may be problematic. Prior art processors may not handle exceptions on instructions produced by decoding a single macro-instruction inefficiently.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
A first aspect of the present invention provides an apparatus. The processor has a plurality of registers. The processor is capable of re-executing at least one selected instruction by backing out of an architectural register state. A second aspect of the present invention provides a method for backing a processor out of an architectural state. The method comprises reassigning a register to a logical operand of an instruction, the register having been assigned to the logical operand in a previous architectural state; and re-executing the instruction.


REFERENCES:
patent: 5797013 (1998-08-01), Mahadevan et al.
patent: 6047370 (2000-04-01), Grochowski
patent: 6076153 (2000-06-01), Grochowski et al.
patent: 6092175 (2000-07-01), Levy et al.
patent: 6182210 (2001-01-01), Akkary et al.
patent: 6205542 (2001-03-01), Grochowski et al.
patent: 6240509 (2001-05-01), Akkary

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