Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-12-30
2001-06-12
Coleman, Eric (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S210000, C712S223000
Reexamination Certificate
active
06247112
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to digital computers and processors and, in particular, is directed to methods and apparatus for executing instructions for manipulating digital data.
Digital video technology is increasingly being incorporated into consumer electronic equipment. This video technology is superior to the analog video technology now used in commercial broadcasting and traditional VCRs because it provides improved picture quality and increased editing flexibility. Conventional digital video signals, however, require undesirably wide channels for transmission and undesirably large amounts of memory for storage. To avoid these problems, digital video signals are often “compressed” prior to use thereby making possible advances such as digital broadcast television, digital satellite television, video teleconferencing, and video mail.
Digital video signal compression reduces the amount of data by removing redundant information from the signal, thereby reducing the amount of data without affecting the quality of an image produced from the decompressed signal. A video signal processor that performs both compression and decompression of video signals is known as a “codec.”
FIG. 1
is a basic flow diagram showing data compression (“encoding”) and data decompression (“decoding”) processes of a prior art codec. For more information regarding the operation of a standard codec, see Stephen J. Solari, Digital Video and Audio Compression (1997), pp. 51-76.
Codecs typically employ some type of computer processor to perform the functions of compression and decompression. Conventional computer central processing units (CPUs) known as “complex instruction set computer” (CISC) processors are characterized by the capability to perform many different types of computer instructions. In particular, CISC processors can perform memory-to-memory instructions with complex memory accesses. In the past, CPUs could execute instructions faster than memory circuits could store or retrieve data. Thus, the complex instructions of CISC processors were used in place of software subroutines, thereby reducing the time that the CPU spent waiting for the memory to deliver instructions and enhancing computer performance.
With increasing memory speeds, however, computer designers have developed “reduced instruction set computer” (RISC) processors that take advantage of the nuances of high-level languages and specially designed hardware architectures. As the name implies, RISC processors use fewer types of instructions than CISC processors. RISC processors achieve high performance by implementing the most common computer instructions directly in hardware, usually at an execution rate of one instruction per clock cycle. Tasks too complex to execute in a single cycle are implemented by programmers by using a series of basic instructions inserted into high-level language instructions (“in-line code”) or by calling a subroutine. For more information on RISC processors, see Kane et al., “MIPS R2000 RISC Architecture”, Prentice Hall, 1992.
RISC architectures also gain speed by “pipelining,” that is, overlapping the execution of instructions which require more than a single clock cycle. In pipelining, instructions that are executed multiple times in a row are divided into discrete portions each requiring one clock cycle and executed in parallel. When the first discrete portion of the first instruction finishes, the second instruction begins execution. With pipelining, each instruction takes the same amount of time to complete, but the overall rate of execution of the instruction set improves.
Designers of special purpose devices, such as, for example, codecs, have incorporated RISC processors into their products to improve performance. The designers often optimize the performance of particular products by extending the normal instruction set of a RISC processor with a set of instructions that are executed repeatedly by a special purpose application program. The present invention provides methods and apparatus for performing bit manipulation that enhance the performance of computer processors by increasing speed. The present invention also provides methods and apparatus for performing bit manipulation that, in particular, improve the performance of digital video codecs.
SUMMARY OF THE INVENTION
Consistent with the present invention, methods for performing and computer-readable media containing instructions for controlling a computer system to perform bit manipulation using a single instruction are disclosed. The method comprises loading N bits from a first register into high order bits of a second register. A subset of least significant bits of a third register are loaded to the low order bits of the second register. All three registers are identified by the single instruction.
A processor for executing a single instruction consistent with the present invention comprises means for loading N bits from a first register into high order bits of a second register and means for loading a subset of least significant bits of a third register to the low order bits of the second register. All three registers are identified by the single instruction.
Furthermore, another method of operating a processor using a single instruction consistent with the present invention comprises the following operations. The processor shifts a value stored in a first register based on a shift value stored in a second register and loads N bits from the shift register to a third register. All three registers are identified by the single instruction.
A processor consistent with the present invention comprises means for executing a single instruction to perform the following operations. The processor includes means for shifting a value stored in a first register based on a shift value stored in a second register and means for loading N bits from the shift register to a third register. All three registers are identified by the single instruction.
A method of transforming a digital data stream into a stream of coefficients representing pixel information of an image is also disclosed. The method comprises loading digital data to a first register of a processor comprising a plurality of registers; identifying a table entry containing run and level based on the digital data; obtaining the run from the table entry using a single instruction identifying registers storing the table entry, a shift value, and the run; obtaining the level from the table entry using a single instruction identifying registers storing the table entry, a shift value, and the level; and storing the run and level to an output register.
REFERENCES:
patent: 5568624 (1996-10-01), Sites et al.
patent: 5963744 (1999-10-01), Slavenburg
patent: 6052522 (2000-04-01), Mattela
Solari, Stephen J., Digital Video and Audio Compression, McGraw-Hill Companies, Inc., 1997, pp. 51-76.
Patterson, David A. and Hennessy, John L., Computer Organization & Design, Morgan Kaufman Publishers, Inc., 1998, pp. 342-399.
“One-to-One Digital Video: Intergrating Encoding and Decoding Technology on One Chip”, available online at http:/www.c-cube.com/technlogy/dvx.html, as of Jan. 8, 1998, pp. 1-19.
“LSI Logic's Single Chip Decoding Engine for DVD Applications”, available online at http:/www.isilogic.com/products/5_6b3.html, as of Jan. 8, 1998, pp. 1-6.
Gwennap, Linley, “New PA-RISC Processor Decodes MPEG Video,” available online at http://hpcc923.external.hp.com/wsg/strategies/parisc3.html, as of Jan. 8, 1998, reprinted from Microprocessor Report: The Insiders' Guide to Microprocessor Hardware, vol. 8, Issue 1, 1994, pp. 1-3.
Imaging Tutorials, Backgrounder: TMS320C80 DSP available at http:/www.precisionimages.com/bgr_c80.html, as of Jan. 8, 1998, pp. 1-4.
Coleman Eric
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Sony Corporation
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