Barrier synchronization mechanism for processors of a...

Details Barrier synchronization mechanism for processors of a... Barrier synchronization mechanism for processors of a...

2006-08-29

2006-08-29

Treat, William M. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C713S375000

Reexamination Certificate

active

07100021

ABSTRACT:
A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronization mechanism that enables synchronization among processors of a column (i.e., different rows) of the systolic array. That is, the barrier synchronization function allows all participating processors within a column to reach a common point within their instruction code sequences before any of the processors proceed.

REFERENCES:
patent: 5434995 (1995-07-01), Oberlin et al.
patent: 5721921 (1998-02-01), Kessler et al.
patent: 5928351 (1999-07-01), Horie et al.
patent: 6101599 (2000-08-01), Wright et al.
patent: 6119215 (2000-09-01), Key et al.
patent: 6173386 (2001-01-01), Key et al.
patent: 6272621 (2001-08-01), Key et al.
patent: 6442669 (2002-08-01), Wright et al.
patent: 6466988 (2002-10-01), Sukegawa et al.
patent: 6505269 (2003-01-01), Potter
patent: 6513108 (2003-01-01), Kerr et al.
patent: 6643763 (2003-11-01), Starke et al.
The Authroitative Dictionary of IEEE Standards Terms; IEEE Press; 7th Edition, 2000, p. 762.
Ghose et al., The Implementing of Low Latency Communication Primitives in the SNOW Protype, Proceedings of the 1997 International Conference on Parallel Processing, IEEE, Aug. 11-15, 1997, pp. 462-469.
U.S. Appl. No. 09/978,640, Marshall et al., filed Oct. 16, 2001.

Affiliated with

Also associated with

Rating

Barrier synchronization mechanism for processors of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Barrier synchronization mechanism for processors of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Barrier synchronization mechanism for processors of a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3700688