Address stage logic for generating speculative address...
Adjustable cycle pipeline system and method
Adjusting thread instruction issue rate based on deviation...
Advanced load address table entry invalidation based on...
Advanced load value check enhancement
Advanced processor scheduling in a multithreaded system
Aggressive store merging in a processor that supports...
Algebraic single instruction multiple data processing
Aliasing data processing registers
Aligning instructions using a variable width alignment...
Aligning load/store data using rotate, mask,...
Aligning load/store data with big/little endian determined...
Aligning precision converted vector data using mask...
Alignment and ordering of vector elements for single...
Alignment and ordering of vector elements for single...
Allocating lower priority interrupt for processing to slave...
Allocating lower priority interrupt for processing to slave...
Allocating registers in a superscalar machine
Allocating resources to partitions in a partitionable computer
Allocation of branch target cache resources in dependence...