Allocating registers in a superscalar machine

Electrical computers and digital processing systems: processing – Instruction decoding

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 1200

Patent

active

059788984

ABSTRACT:
A register allocator is provided including a plurality of N allocatable memory cells arranged in B banks having N/B rows each so that each of the N allocatable memory cells is capable of storing a register identifier. The register allocator includes a plurality of M parallel execution write data ports coupled to the plurality of N allocatable memory cells so as to be capable of writing a de-allocated register identifier to a first associated memory cell and a plurality of M parallel execution read data ports coupled to the plurality of N allocatable memory cells so as to be capable of reading an allocated register identifier from a second associated memory cell. The register allocator includes a plurality of M (N/B)-bit write enable ports coupled to the plurality of N allocatable memory cells by N/B 1-bit write entry ports and a plurality of M (N/B)-bit read enable ports coupled to the plurality of N allocatable memory cells by N/B 1-bit read entry ports. The register allocator also includes a decoded (B-.delta..sub.1B +N/B)-bit head pointer decoded in a write decoder and coupled to the plurality of M (N/B)-bit write enable ports and a decoded (B-.delta..sub.1B +N/B)-bit tail pointer decoded in a read decoder and coupled to the plurality of M (N/B)-bit read enable ports. Up to M of the plurality of N allocatable memory cells are allocatable on a first-in-first-out basis determined by respective positions of the decoded (B-.delta..sub.1B +N/B)-bit head pointer a nd the decoded (B-.delta..sub.1B +N/B)-bit tail pointer. The respective positions of the decoded (B-.delta..sub.1B +N/B)-bit head pointer and the decoded (B-.delta..sub.1B +N/B)-bit tail pointer are separately incrementable.

REFERENCES:
patent: 5367651 (1994-11-01), Smith et al.
patent: 5367684 (1994-11-01), Smith et al.
patent: 5890000 (1999-03-01), Aizikowitz et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Allocating registers in a superscalar machine does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Allocating registers in a superscalar machine, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Allocating registers in a superscalar machine will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2150818

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.