Allocating lower priority interrupt for processing to slave...

Details Allocating lower priority interrupt for processing to slave... Allocating lower priority interrupt for processing to slave...

2008-07-08

2008-07-08

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Branching

C710S260000

Reexamination Certificate

active

07398378

ABSTRACT:
In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.

REFERENCES:
patent: 6711643 (2004-03-01), Park et al.
patent: 6772241 (2004-08-01), George et al.
patent: 2000-305917 (2000-11-01), None

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