Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2004-07-23
2009-10-20
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
07606995
ABSTRACT:
Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.
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Herrell Russ
Kaufman, Jr. Gerald J.
Morrison John A.
Chan Eddie P
Fennema Robert E
Hewlett--Packard Development Company, L.P.
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